Semiconductor memories, such as, for example, DRAMs (Dynamic Random Access Memories), include a cell array and an addressing periphery. Individual memory cells are arranged in the cell array.
The cell array of a DRAM chip contains a matrix of memory cells which are arranged in the form of rows and columns and are addressed by word lines and bit lines. Data are read from the memory cells or data are written to the memory cells by the activation of suitable word lines and bit lines.
A memory cell of a DRAM usually contains a transistor connected to a capacitor. The transistor comprises, inter alia, two diffusion regions which are separated from one another by a channel controlled by a gate. One diffusion region is referred to as the drain region and the other diffusion region is referred to as the source region.
One of the diffusion regions is connected to a bit line. The other diffusion region is connected to a capacitor and the gate is connected to a word line. By the application of suitable voltages to the gate, the transistor is controlled in such a way that a current flow between the diffusion regions is switched on and off by the channel.
The advancing miniaturization of memory components means that the integration density continuously increases. The continuous increase in the integration density means that the area available per memory cell decreases ever further. This has the result that the selection transistor and the storage capacitor of a memory cell are subject to continual reduction of their geometrical dimensions.
Ongoing endeavours to reduce the size of the memory devices promote the design of DRAMs with a high density and a small characteristic size, such as a small area per memory cell. In order to fabricate memory cells which require a small surface region, use is made of smaller components, such as, for example, smaller capacitors. The use of capacitors reduced in size results in a lower storage capacitance of the individual capacitor, which may in turn adversely affect the functionality and usability of the memory device.
For example, sense amplifiers require a sufficient signal level for reliably reading out the information stored in the memory cells. The ratio of the storage capacitance to the bit line capacitance is crucial in determining a sufficient signal level. If the storage capacitance is too low, this ratio may be too small for generating an adequate signal for driving the sense amplifier. A lower storage capacitance likewise requires a higher refresh frequency.
Furthermore, it is known to arrange the selection transistor as a vertical selection transistor in the trench of the trench capacitor or above the trench of the trench capacitor. This likewise makes it possible to utilize the available substrate surface in a space-saving manner for memory cells.
In dynamic random access memories (DRAMs), nowadays use is made predominantly of so-called one-transistor cells. The latter comprise a storage capacitor and a selection transistor, which connects the storage electrode to a bit line. The storage capacitor is nowadays often formed as a so-called trench capacitor or stacked capacitor. For this purpose, usually a trench is etched into the substrate and a dielectric and an inner storage electrode are introduced into the trench.
Memory cells are known in which the selection transistor is arranged on the planar surface of the substrate, beside the trench capacitor. In order to realize a so-called folded bit line concept, such a memory cell requires a chip area of at least 8 F2, where F represents the minimum periodic feature size of the lithographic imaging. A folded bit line concept makes it possible, for example, to evaluate very small signal levels which are fed from a memory cell to a sense amplifier via a bit line.
In order to ensure a folded bit line concept with a cell area of at most 8 F2, a word line is permitted to have a maximum width of 1 F. Consequently, this means that a planar selection transistor can have a maximum channel length of 1 F. For subsequent technology generations, the lithography dimension F may be smaller than 100 nm so that corresponding selection transistors would have a channel length of less than 100 nm. This may result in the corresponding selection transistors having increased leakage currents due to their short channel length. Leakage currents can lead to a loss of the information stored in the memory cell.
Consequently, the problem exists of specifying a scalable memory cell concept with a maximum cell area of 8 F2. One concern is that the electrical properties of the selection transistor and the corresponding interconnection as a folded bit line concept are not impaired. In addition to a channel length that is not too short, what should be avoided, in particular, are a decrease in the current-carrying capacity of the selection transistor and the mutual influencing of memory cells and a potential loss of information.
The channel length of the selection transistor may be, for example, a vertical selection transistor such that leakage currents are reduced or avoided. Various cell concepts with vertical selection transistors and various capacitor types have already been proposed.
If the selection transistor is formed with a minimum transistor width of 1 F, then this leads to an increase in the channel resistance, if the channel length is kept constant, since the ratio of transistor length to transistor width becomes ever greater as F decreases. This poses a problem, for instance, in concepts with a selection transistor whose channel width is formed merely with 1 F. There are examples of known concepts which solve this problem by a gate enclosing the active region. As a result, the channel width is formed larger than 1 F, for example, as described in U.S. Pat. No. 5,519,236, which, however does not describe a folded bit line concept.
The patterning and the alignment of the individual components with respect to one another is a problem in the realization of corresponding word lines which connect the gate electrodes enclosing the active region to one another. Since the gate electrodes enclosing the active region must be at a sufficient distance perpendicular to the word line in order to be insulated from one another. In known concepts, there is the need for lithographic patterning of the word line, as is carried out, for example, in U.S. Pat. No. 5,519,236. Due to the complicated alignment required, the lithographic patterning of the word lines leads to increased process costs and an increased space requirement, since it is necessary to comply with corresponding safety margins during the alignment and patterning.
A further group of cell concepts prevents the electrical connection of the active region, which leads to floating body effects. Floating body effects result if the active region, apart from the introduced source and drain regions, is insulated and electrical connection of the body (substrate) is not provided. Floating body effects limit the electrical properties, which, if appropriate, prevent the selection transistor from closing. As a result, a loss of information stored in the cell can occur due to leakage currents.